MC68HC08AS32A Datasheet, PDF (177/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
Functional Description
bit automatically goes into the least significant bit position of the transmit shift
register. A logic 1 stop bit goes into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR
transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR
can accept new data from the internal data bus. If the SCI transmit interrupt enable
bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU interrupt
request.
When the transmit shift register is not transmitting a character, the PTE0/TxD pin
goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in
SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the
port E pins.
13.4.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift
register with a break character. A break character contains all logic 0s and has no
start, stop, or parity bit. Break character length depends on the M bit in SCC1. As
long as SBK is at logic 1, transmitter logic continuously loads break characters into
the transmit shift register. After software clears the SBK bit, the shift register
finishes transmitting the last break character and then transmits at least one
logic 1. The automatic logic 1 at the end of a break character guarantees the
recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by eight or nine
logic 0 data bits and a logic 0 where the stop bit should be.
Receiving a break character has these effects on SCI registers:
• Sets the framing error bit (FE) in SCS1
• Sets the SCI receiver full bit (SCRF) in SCS1
• Clears the SCI data register (SCDR)
• Clears the R8 bit in SCC3
• Sets the break flag bit (BKF) in SCS2
• May set the overrun (OR), noise flag (NF), parity error (PE), or reception in
progress flag (RPF) bits
13.4.2.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle
character length depends on the M bit in SCC1. The preamble is a synchronizing
idle character that begins every transmission.
If the TE bit is cleared during a transmission, the PTE0/TxD pin becomes idle after
completion of the transmission in progress. Clearing and then setting the TE bit
during a transmission queues an idle character to be sent after the character
currently being transmitted.
MC68HC08AS32A — Rev. 1
MOTOROLA
Serial Communications Interface (SCI)
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Data Sheet
177