MC68HC08AS32A Datasheet, PDF (229/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Queuing Transmission Data
SPTE SPTIE SPE
SPRIE SPRF
SPI TRANSMITTER
CPU INTERRUPT REQUEST
ERRIE
MODF
OVRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
Figure 15-11. SPI Interrupt Request Generation
WRITE TO SPDR ¹
3
8
SPTE
2
5
10
SPSCK (CPHA:CPOL = 1:0)
MOSI
SPRF
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
654321
654321
654
BYTE 1
BYTE 2
BYTE 3
4
9
READ SPSCR
6
11
READ SPDR
7
12
1 CPU WRITES BYTE 1 TO SPDR, CLEARING
SPTE BIT.
2 BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER,
SETTING SPTE BIT.
3 CPU WRITES BYTE 2 TO SPDR, QUEUEING
BYTE 2 AND CLEARING SPTE BIT.
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT
SHIFT REGISTER TO RECEIVE DATA REGISTER,
SETTING SPRF BIT.
5 BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING
SPTE BIT.
6 CPU READS SPSCR WITH SPRF BIT SET.
10 BYTE 3 TRANSFERS FROM TRANSMIT
DATA REGISTER TO SHIFT REGISTER,
SETTING SPTE BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
7 CPU READS SPDR, CLEARING SPRF BIT.
12 CPU READS SPDR, CLEARING SPRF BIT.
8 CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
9 SECOND INCOMING BYTE TRANSFERS FROM
SHIFT REGISTER TO RECEIVE DATA REGISTER,
SETTING SPRF BIT.
Figure 15-12. SPRF/SPTE CPU Interrupt Timing
The transmit data buffer allows back-to-back transmissions without the slave
precisely timing its writes between transmissions as in a system with a single data
buffer. Also, if no new data is written to the data buffer, the last value contained in
the shift register is the next data word to be transmitted.
For an idle master or idle slave that has no data loaded into its transmit buffer, the
SPTE is set again no more than two bus cycles after the transmit buffer empties
MC68HC08AS32A — Rev. 1
MOTOROLA
Serial Peripheral Interface (SPI)
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Data Sheet
229