MC68HC08AS32A Datasheet, PDF (112/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
5.8 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules
can be cleared during the break state. The BCFE bit in the SIM break flag control
register (SBFCR) enables software to clear status bits during the break state. (See
14.7.3 SIM Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a logic 1 to the
BCFE bit. If a status bit is cleared during the break state, it remains cleared when
the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With
BCFE at logic 0 (its default state), software can read and write the PLL control
register during the break state without affecting the
PLLF bit.
5.9 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most
critical PLL design parameters. Proper design and use of the PLL ensure the
highest stability and lowest acquisition/lock times.
5.9.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction
time, within specified tolerances, of the system to a step input. In a PLL, the step
input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance
usually is specified as a percent of the step input or when the output settles to the
desired value plus or minus a percent of the frequency change. Therefore, the
reaction time is constant in this definition, regardless of the size of the step input.
For example, consider a system with a 5% acquisition time tolerance. If a
command instructs the system to change from 0 Hz to 1 MHz, the acquisition time
is the time taken for the frequency to reach 1 MHz ±50 kHz. 50 kHz = 5% of the
1-MHz step input. If the system is operating at 1 MHz and suffers a –100-kHz noise
hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz.
5 kHz = 5% of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system takes to
reduce the error between the actual output and the desired output to within
specified tolerances. Therefore, the acquisition time or lock time vary according to
the original error in the output. Minor errors may not even be registered. Typical
PLL applications prefer to use this definition because the system requires the
output frequency to be within a certain tolerance of the desired frequency
regardless of the size of the initial error.
Data Sheet
112
Clock Generator Module (CGM)
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MC68HC08AS32A — Rev. 1
MOTOROLA