MC68HC08AS32A Datasheet, PDF (104/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
For proper operation,
f_VRS – f_VCLK
≤ -^f--^N---^O----^M--
2
8. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG), program
the binary equivalent of N.
b. In the lower four bits of the PLL programming register (PPG), program
the binary equivalent of L.
5.3.2.5 Special Programming Exceptions
The programming method described in 5.3.2.4 Programming the PLL does not
account for two possible exceptions. A value of zero for N or L is meaningless when
used in the equations given. To account for these exceptions:
• A zero value for N is interpreted exactly the same as a value of one.
• A zero value for L disables the PLL and prevents its selection as the source
for the base clock. (See 5.3.3 Base Clock Selector Circuit.)
5.3.3 Base Clock Selector Circuit
This circuit is used to select either the crystal clock (CGMXCLK) or the VCO clock
(CGMVCLK) as the source of the base clock (CGMOUT). The two input clocks go
through a transition control circuit that waits up to three CGMXCLK cycles and
three CGMVCLK cycles to change from one clock source to the other. During this
time, CGMOUT is held in stasis. The output of the transition control circuit is then
divided by two to correct the duty cycle. Therefore, the bus clock frequency, which
is one-half of the base clock frequency, is one-fourth the frequency of the selected
clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source if the PLL
is not turned on. The PLL cannot be turned off if the VCO clock is selected. The
PLL cannot be turned on or off simultaneously with the selection or deselection of
the VCO clock. The VCO clock also cannot be selected as the base clock source
if the factor L is programmed to a zero. This value would set up a condition
inconsistent with the operation of the PLL, so that the PLL would be disabled and
the crystal clock would be forced as the source of the base clock.
Data Sheet
104
Clock Generator Module (CGM)
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MC68HC08AS32A — Rev. 1
MOTOROLA