MC68HC08AS32A Datasheet, PDF (223/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Transmission Formats
SCK CYCLE #
FOR REFERENCE
SCK CPOL = 0
1
2
3
4
5
6
7
8
SCK CPOL =1
MOSI
FROM MASTER
MISO
FROM SLAVE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
SS TO SLAVE
CAPTURE STROBE
Figure 15-7. Transmission Format (CPHA = 1)
15.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), transmissions are started
by a software write to the SPDR ($0012). CPHA has no effect on the delay to the
start of the transmission, but it does affect the initial state of the SCK signal.
When CPHA = 0, the SCK signal remains inactive for the first half of the first SCK
cycle. When CPHA = 1, the first SCK cycle begins with an edge on the SCK line
from its inactive to its active level. The SPI clock rate (selected by SPR1–SPR0)
affects the delay from the write to SPDR and the start of the SPI transmission. (See
Figure 15-8.) The internal SPI clock in the master is a free-running derivative of the
internal MCU clock. It is only enabled when both the SPE and SPMSTR bits
(SPCR) are set to conserve power. SCK edges occur halfway through the low time
of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where
the write to the SPDR will occur relative to the slower SCK. This uncertainty causes
the variation in the initiation delay shown in Figure 15-8. This delay will be no
longer than a single SPI bit time. That is, the maximum delay between the write to
SPDR and the start of the SPI transmission is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles
for DIV128.
MC68HC08AS32A — Rev. 1
MOTOROLA
Serial Peripheral Interface (SPI)
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Data Sheet
223