MC68HC08AS32A Datasheet, PDF (81/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Controller-Digital (BDLC-D)
BDLC Protocol Handler
BDRxD
TO PHYSICAL INTERFACE
BDTxD
DLOOP FROM BCR2
LOOPBACK CONTROL
LOOPBACK
MULTIPLEXER
STATE MACHINE
Rx SHIFT REGISTER
Rx SHADOW REGISTER
8
Tx SHIFT REGISTER
Tx SHADOW REGISTER
8
TO CPU INTERFACE AND Rx/Tx BUFFERS
Figure 4-15. BDLC Protocol Handler Outline
4.5.4 Digital Loopback Multiplexer
The digital loopback multiplexer connects RxD to either BDTxD or BDRxD,
depending on the state of the DLOOP bit in the BCR2 register (see 4.6.3 BDLC
Control Register 2).
4.5.5 State Machine
All of the functions associated with performing the protocol are executed or
controlled by the state machine. The state machine is responsible for framing,
collision detection, arbitration, CRC generation/checking, and error detection. The
following sections describe the BDLC’s actions in a variety of situations.
4.5.5.1 4X Mode
The BDLC can exist on the same J1850 bus as modules which use a special 4X
(41.6 kbps) mode of J1850 variable pulse width modulation (VPW) operation. The
BDLC cannot transmit in 4X mode, but can receive messages in 4X mode, if the
RX4X bit is set in BCR2 register. If the RX4X bit is not set in the BCR2 register, any
4X message on the J1850 bus is treated as noise by the BDLC and is ignored.
MC68HC08AS32A — Rev. 1
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
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Data Sheet
81