MC68HC08AS32A Datasheet, PDF (63/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Data Sheet — MC68HC08AS32A
Section 4. Byte Data Link Controller-Digital (BDLC-D)
4.1 Introduction
The byte data link controller (BDLC) provides access to an external serial
communication multiplex bus, operating according to the Society of Automotive
Engineers (SAE) J1850 protocol.
4.2 Features
Features of the BDLC module include:
• SAE J1850 class B data communications network interface compatible and
ISO compatible for low speed (<125 kbps) serial data communications in
automotive applications
• 10.4 kbps variable pulse width (VPW) bit format
• Digital noise filter
• Collision detection
• Hardware cyclical redundancy check (CRC) generation and checking
• Two power-saving modes with automatic wakeup on network activity
• Polling and CPU interrupts available
• Block mode receive and transmit supported
• Supports 4X receive mode, 41.6 kbps
• Digital loopback mode
• Analog loopback mode
• In-frame response (IFR) types 0, 1, 2, and 3 supported
4.3 Functional Description
Figure 4-2 shows the organization of the BDLC module. The CPU interface
contains the software addressable registers and provides the link between the
CPU and the buffers. The buffers provide storage for data received and data to be
transmitted onto the J1850 bus. The protocol handler is responsible for the
encoding and decoding of data bits and special message symbols during
transmission and reception. The MUX interface provides the link between the
BDLC digital section and the analog physical interface. The wave shaping, driving,
and digitizing of data is performed by the physical interface.
MC68HC08AS32A — Rev. 1
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
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Data Sheet
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