MC68HC08AS32A Datasheet, PDF (259/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface (TIM)
I/O Registers
NOTE:
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1 and clear output on compare is selected, setting
the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals
to 100%. As Figure 16-9 shows, the CHxMAX bit takes effect in the cycle after
it is set or cleared. The output stays at 100% duty cycle level until the cycle after
CHxMAX is cleared.
The 100% PWM duty cycle is defined as a continuous high level if the PWM polarity
is 1 and a continuous low level if the PWM polarity is 0. Conversely, a 0% PWM
duty cycle is defined as a continuous low level if the PWM polarity is 1 and a
continuous high level if the PWM polarity is 0.
OVERFLOW
OVERFLOW
PERIOD
OVERFLOW
OVERFLOW
OVERFLOW
TCHx
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 16-9. CHxMAX Latency
16.8.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input
capture function or the output compare value of the output compare function. The
state of the TIM channel registers after reset is unknown.
In input capture mode (MSxB–MSxA = 0–0), reading the high byte of the TIM
channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is
read.
In output compare mode (MSxB–MSxA ≠ 0–0), writing to the high byte of the TIM
channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is
written.
MC68HC08AS32A — Rev. 1
MOTOROLA
Timer Interface (TIM)
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Data Sheet
259