MC68HC08AS32A Datasheet, PDF (147/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Mask Options
Mask Option Registers (MORA and MORB)
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 6. Computer Operating
Properly (COP).)
1 = COP module disabled
0 = COP module enabled
Address: $FE09
Bit 7
6
5
4
3
2
1
Bit 0
Read: EEDIVCLK
AS32A
Write:
Reset:
= Unimplemented
Unaffected by reset
Figure 10-2. Mask Option Register 2 (MORB)
NOTE:
EEDIVCLK — EEPROM Timebase Divider Clock Select Bit
EDIVCLK selects the reference clock source for the EERPOM timebase divider.
See 2.5.2.4 EEPROM Timebase Divider Register.
1 = CPU bus clock drives the EEPROM timebase divider
0 = CGMXCLK drives the EEPROM timebase divider
AS32A — Device Indicator
This bit is used to distinguish a MC68HC08AS32A from older non-’A’ suffix
versions.
1 = ‘A’ version
0 = Non ‘A’ version
Extra care should be exercised when selecting mask option registers since other
M68HC08 Family parts may have different options. If in doubt, check with your
local field applications representative.
MC68HC08AS32A — Rev. 1
MOTOROLA
Mask Options
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Data Sheet
147