MC68HC08AS32A Datasheet, PDF (231/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI During Break Interrupts
To exit wait mode when an overflow condition occurs, enable the OVRF bit to
generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE).
(See 15.7 Interrupts.)
15.10.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions. SPI operation resumes after the
MCU exits stop mode. If stop mode is exited by reset, any transfer in progress is
aborted and the SPI is reset.
15.11 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules
can be cleared during the break state. The BCFE bit in the SIM break flag control
register (SBFCR, $FE03) enables software to clear status bits during the break
state. (See 14.7.3 SIM Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a logic 1 to the
BCFE bit. If a status bit is cleared during the break state, it remains cleared when
the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With
BCFE at logic 0 (its default state), software can read and write I/O registers during
the break state without affecting status bits. Some status bits have a 2-step
read/write clearing procedure. If software does the first step on such a bit before
the break, the bit cannot change during the break state as long as BCFE is at logic
0. After the break, doing the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a
write to the data register in break mode will not initiate a transmission nor will this
data be transferred into the shift register. Therefore, a write to the SPDR in break
mode with the BCFE bit cleared has no effect.
15.12 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel I/O port.
• MISO — Data received
• MOSI — Data transmitted
• SPSCK — Serial clock
• SS — Slave select
• V_SS — Clock ground
The SPI has limited inter-integrated circuit (I²C) capability (requiring software
support) as a master in a single-master environment. To communicate with I²C
peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI
MC68HC08AS32A — Rev. 1
MOTOROLA
Serial Peripheral Interface (SPI)
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Data Sheet
231