MC68HC08AS32A Datasheet, PDF (153/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Programmable Interrupt Timer (PIT)
I/O Registers
PPS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to
the PIT counter as Table 11-1 shows. Reset clears the PPS[2:0] bits.
Table 11-1. Prescaler Selection
PPS[2:0]
000
001
010
011
100
101
110
111
PIT Clock Source
Internal bus clock ÷1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Internal bus clock ÷ 64
11.7.2 PIT Counter Registers
The two read-only PIT counter registers contain the high and low bytes of the value
in the PIT counter. Reading the high byte (PCNTH) latches the contents of the low
byte (PCNTL) into a buffer. Subsequent reads of PCNTH do not affect the latched
PCNTL value until PCNTL is read. Reset clears the PIT counter registers. Setting
the PIT reset bit (PRST) also clears the PIT counter registers.
NOTE:
If you read PCNTH during a break interrupt, be sure to unlatch PCNTL by reading
PCNTL before exiting the break interrupt. Otherwise, PCNTL retains the value
latched during the break.
Address: $004C
Bit 7
6
5
4
3
2
Read: Bit 15
14
13
12
11
10
1
Bit 0
9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
Address: $004D
Bit 7
6
5
4
3
2
Read: Bit 15
14
13
12
11
10
Write:
Reset: 0
0
0
0
0
0
= Unimplemented
1
Bit 0
9
Bit 8
0
0
Figure 11-4. PIT Counter Registers (PCNTH–PCNTL)
MC68HC08AS32A — Rev. 1
MOTOROLA
Programmable Interrupt Timer (PIT)
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Data Sheet
153