N25Q032A13E1241F Datasheet, PDF (98/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Figure 60. Read Lock Register instruction and data-out sequence DIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
C
DQ0
Instruction
24-Bit Address*
Lock Register Out
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0
DQ1
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1
*Address bits A23 and A22 are “Don’t Care.”
9.2.17
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
Except for the parallelizing of the instruction code, the address and the input data on the two
pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write to Lock
Register (WRLR) instruction of the Extended SPI protocol.
Figure 61. Write to Lock Register instruction sequence DIO-SPI
S
C
DQ0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 12 13 14 15
Instruction
*24-bit Address
Lock Register In
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0
DQ1
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1
9.2.18
*Address bits A23 and A22 are “Don’t Care.”
Read Flag Status Register
The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be
read.
Except for the parallelizing of the instruction code and the output data on the two pins DQ0
and DQ1, the instruction functionality is exactly the same as the Read Flag Status Register
(RFSR) instruction of the Extended SPI protocol.
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