N25Q032A13E1241F Datasheet, PDF (12/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Description
1
Description
N25Q032 - 3 V
The N25Q032 is a 32 Mbit (4Mb x 8) serial Flash memory, with advanced write protection
mechanisms. It is accessed by a high speed SPI-compatible bus and features the possibility
to work in XIP (“eXecution in Place”) mode.
The N25Q032 supports innovative, high-performance quad/dual I/O instructions, these new
instructions allow to double or quadruple the transfer bandwidth for read and program
operations.
Furthermore the memory can be operated with 3 different protocols:
z Standard SPI (Extended SPI protocol)
z Dual I/O SPI
z Quad I/O SPI
The Standard SPI protocol is enriched by the new quad and dual instructions (Extended SPI
protocol). For Dual I/O SPI (DIO-SPI) all the instructions codes, the addresses and the data
are always transmitted across two data lines. For Quad I/O SPI (QIO-SPI) the instructions
codes, the addresses and the data are always transmitted across four data lines thus
enabling a tremendous improvement in both random access time and data throughput.
The memory can work in “XIP mode”, that means the device only requires the addresses
and not the instructions to output the data. This mode dramatically reduces random access
time thus enabling many applications requiring fast code execution without shadowing the
memory content on a RAM.
The XIP mode can be used with QIO-SPI, DIO-SPI, or Extended SPI protocol, and can be
entered and exited using different dedicated instructions to allow maximum flexibility: for
applications required to enter in XIP mode right after power up of the device, this can be set
as default mode by using dedicated Non Volatile Register (NVR) bits.
Another feature is the ability to pause and resume program and erase cycles by using
dedicated Program/Erase Suspend and Resume instructions.
The N25Q032 memory offers the following additional features to be configured by using the
Non Volatile Configuration Register (NVCR) for default /Non-Volatile settings or by using the
Volatile and Volatile Enhanced Configuration Registers for Volatile settings:
z the number of dummy cycles for fast read instructions (single, dual and, quad I/O)
according to the operating frequency
z the output buffer impedance
z the type of SPI protocol (extended SPI, DIO-SPI or QIO-SPI)
z the required XIP mode
z the Hold (Reset) functionality enabling/disabling
z the Wrap mode enabling/disabling.
The memory is organized as 64 (64-Kbyte) main sectors that are further divided into 16
subsectors each (1024 subsectors in total). The memory can be erased a 4-KByte
subsector at a time, a 64-KByte sector at a time, or as a whole.
The memory can be write protected by software using a mix of volatile and non-volatile
protection features, depending on the application needs. The protection granularity is of 64-
Kbyte (sector granularity) for volatile protections.
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