N25Q032A13E1241F Datasheet, PDF (56/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Table 15. Extended Device ID table (first byte)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Reserved Reserved Reserved
VCR XIP bit setting:
0 = required,
1 = not required
Hold/Reset function:
0 = HOLD,
1 = Reset
Addressing:
0 = by Byte,
Bit 1 Bit 0
Architecture:
00 = Uniform,
Figure 10. Read identification instruction and data-out sequence
S
C
DQ0
DQ1
9.1.2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31
Instruction
High Impedance
Manufacturer identification
Device identification
UID
MSB
15 14 13
MSB
3210
MSB
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents at that
address are shifted out on Serial Data output (DQ1), each bit being shifted out at a
maximum frequency fR during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase or Program cycle is in progress, is rejected without having any
effects on the cycle that is in progress.
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