N25Q032A13E1241F Datasheet, PDF (66/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes. See Table 31.: AC
Characteristics.
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register
and the Flag Status Register may be read to check if the internal modify cycle is finished. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0 and TB) bits is not executed.
Page Program cycle can be paused by mean of Program/Erase Suspend (PES) instruction
and resumed by mean of Program/Erase Resume (PER) instruction.
Figure 21. Page Program Instruction Sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
*24-bit Address
Data byte 1
DQ0
23 22 21
321076543210
MSB
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data byte 2
Data byte 3
Data byte 256
DQ0
7654321076543210
76543210
MSB
MSB
MSB
*Address bits A23 and A22 are “Don’t Care.”
66/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.