N25Q032A13E1241F Datasheet, PDF (102/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Figure 68. Read Volatile Enhanced Configuration Register instruction sequence
DIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11
C
Instruction
Volatile Enhanced
Configuration Register Out
Byte
Byte
DQ0
6420 6420
DQ1
7531 7531
9.2.25
Write Volatile Enhanced Configuration Register
The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new
values to be written to the Volatile Enhanced Configuration register. Before it can be
accepted, a write enable (WREN) instruction must previously have been executed.
Except for the parallelizing of the instruction code and the input data on the two pins DQ0
and DQ1, the instruction functionality is exactly the same as the Write Volatile Enhanced
Configuration Register (WRVECR) instruction of the Extended SPI protocol.
Figure 69. Write Volatile Enhanced Configuration Register instruction sequence
DIO-SPI
S
C
DQ0
01234567
Instruction
Volatile Enhanced
Configuration Register In
Byte
6420
DQ1
7531
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