N25Q032A13E1241F Datasheet, PDF (63/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Instructions
9.1.9
Read OTP (ROTP)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a configurable
number of dummy clock cycles. Each bit is latched in on the rising edge of Serial Clock (C).
Then the memory contents at that address are shifted out on Serial Data output (DQ1).
Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock
(C). The address is automatically incremented to the next higher address after each byte of
data is shifted out.
There is no rollover mechanism with the Read OTP (ROTP) instruction. This means that the
Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read. All other
bytes outside the OTP area are “Don’t Care.”
The Read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read OTP (ROTP)
instruction issued while an Erase or Program cycle is in progress, is rejected without having
any effect on the cycle that is in progress.
Figure 18. Read OTP instruction and data-out sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction
24-bit address
DQ0
DQ1
High Impedance
23 22 21
3210
S
C
DQ0
DQ1
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy cycles
76543210
DATA OUT 1
76543210
MSB
DATA OUT n
765432107
MSB
MSB
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