N25Q032A13E1241F Datasheet, PDF (36/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Volatile and Non Volatile Registers
N25Q032 - 3 V
Table 3. Non-Volatile Configuration Register
Bit
Parameter Value
Description
NVCR<5>
Reserved x
Don’t Care
NVCR<4>
NVCR<3>
Reset/Hold ⁰
disable
1
Quad Input ⁰
Command ₁
disabled
enabled (default)
enabled
disabled (default)
NVCR<2>
Dual Input ⁰
Command ₁
enabled
disabled (default)
NVCR<1:0>
Reserved
xx
Don't care
Note
Default value = 1
Disable Pad Hold/Reset functionality
Enable command on four input lines
Enable command on two input lines
Default value = "11"
6.2.1
Dummy clock cycles NV configuration bits (NVCR bits from 15 to 12)
The bits from 15 to 12 of the Non Volatile Configuration register store the default settings for
the dummy clock cycles number after the fast read instructions (in all the 3 available
protocols). The dummy clock cycles number can be set from 1 up to 15 as described here,
according to operating frequency (the higher is the operating frequency, the bigger must be
the dummy clock cycle number) to optimize the fast read instructions performance.
The default values of these bits allow the memory to be safely used with fast read
instructions at the maximum frequency (108 MHz). Please note that if the dummy clock
number is not sufficient for the operating frequency, the memory reads wrong data.
Table 4.
Maximum operative frequency by dummy clock cycles
Maximum allowed frequency (MHz) ⁽¹⁾
Dummy Clock
FASTREAD
DOFR
DIOFR
QOFR
QIOFR
1
54
50
39
43
20
2
95
85
59
56
39
3
105
95
75
70
49
4
108
105
88
83
59
5
108
108
94
94
69
6
108
108
105
105
78
7
108
108
108
108
86
8
108
108
108
108
95
9
108
108
108
108
105
10
108
108
108
108
108
1. All the values are guaranteed by characterization and not 100% tested in production
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