N25Q032A13E1241F Datasheet, PDF (30/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Operating features
N25Q032 - 3 V
5.3.7
5.3.8
5.3.9
Active Power and Standby Power modes
Exactly as in Extended SPI protocol, when Chip Select (S) is Low, the device is selected,
and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but
could remain in the Active Power mode until all internal (Program, Erase, Write) Cycles
have completed. The device then goes in to the Standby Power mode. The device
consumption drops to ICC1.
HOLD (or Reset) condition
The HOLD (Hold) feature (or Reset feature, for parts having the reset functionality instead of
hold) is disabled in QIO-SPI protocol when the device is selected: the Hold (or Reset)/ DQ3
pin always behaves as an I/O pin (DQ3 function) when the device is deselected. For parts
with reset functionality, it is still possible to reset the memory when it is deselected (C signal
high).
VPP pin Enhanced Supply Voltage feature
It is possible in the QIO-SPI protocol to use the VPP pin as an enhanced supply voltage, but
the intention to use VPP as accelerated supply voltage must be declared by setting bit 3 of
the VECR to 0.
In this case, to accelerate the Program cycle the VPP pin must be raised to VPPH after the
device has received the last data to be programmed within 200ms. If the VPP is not raised
within 200ms, the program operation starts with the standard internal cycle speed as if the
Vpp high voltage were not used, and a flag error appears on Flag Status Register bit 3".
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