N25Q032A13E1241F Datasheet, PDF (75/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Instructions
9.1.20
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the
entire duration of the sequence.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is ignored if one or more sectors are hardware or software
protected. The Bulk Erase (BE) cycle cannot be paused by a Program Erase Suspend
(PES) instruction.
Figure 30. Bulk Erase instruction sequence
S
C
DQ0
01234567
Instruction
9.1.21
Note:
AI13743
Program/Erase Suspend
The Program/Erase Suspend instruction allows the controller to interrupt a Program or an
Erase instruction, in particular: Sector Erase, Subsector Erase, Page Program, Dual Input
Page Program, Dual Input Extended Page Program, Quad Input Page Program and Quad
Input Extended Page Program instructions can be suspended and resumed.
Bulk Erase, Write Status Register, Write Non Volatile Configuration Register, and Program
OTP cannot be suspended.
After a Program/Erase Suspend instruction the bit 2 of the Flag Status register is
immediately set to 1 and, after a latency time, both the WIP bit of the Status Register and
the Program/Erase controller bit (Not WIP) of the Flag Status Register are cleared (to 0 and
to 1 respectively).
The Suspended state is reset if a power-off is performed or after resume. After a sector
erase instruction has been suspended, another erase instruction is not allowed; however, it
is possible to perform program and reading instructions on all the sectors except the one
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