N25Q032A13E1241F Datasheet, PDF (71/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Instructions
S
C
DQ0
DQ1
DQ2
Figure 25. Quad Input Extended Fast Program instruction sequence
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Instruction
Don’t Care
Don’t Care
*24-bit Address
Data In
Data In
Data In
1
2
3
4
5
6
7
20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0
21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1
22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
DQ3
9.1.17
‘1’
23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
MSB MSB MSB MSB MSB MSB MSB
*Address bits A23 and A22 are “Don’t Care.”
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded, the device sets the Write Enable Latch (WEL) bit.
The Program OTP instruction is entered by driving Chip Select (S) Low, followed by the
instruction opcode, three address bytes and at least one data byte on Serial Data input
(DQ0). Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Program OTP instruction is not executed.
There is no rollover mechanism with the Program OTP (POTP) instruction. This means that
the Program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program,
once all 65 bytes have been latched in, any following byte will be discarded.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Program OTP cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is completed. At
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is
reset. Alternately, it is possible to read the Flag Status Register to check if the internal
modify cycle is finished.
Bit 0 of the OTP control byte, that is byte 64, is used to permanently lock the OTP memory
array.
z When bit 0 of byte 64 = '1', the 64 bytes of the OTP memory array can be programmed.
z When bit 0 of byte 64 = '0', the 64 bytes of the OTP memory array are read-only and
cannot be programmed anymore.
Once a bit of the OTP memory has been programmed to '0', it can no longer be set to '1'.
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