N25Q032A13E1241F Datasheet, PDF (94/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Figure 52. Program OTP instruction sequence DIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
C
Instruction
24-Bit Address
Data Byte 1 Data Byte 2 Data Byte n
DQ0
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
DQ1
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
9.2.9
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must have been executed
previously.
Except for parallelizing the instruction code and the address on pins DQ0 and DQ1, the
instruction functionality is the same as the Subsector Erase (SSE) instruction of the
Extended SPI protocol.
Figure 53. Subsector Erase instruction sequence DIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
DQ0
Inst ruct ion
*24-bit Address
22 20 18 16 14 12 10 8 6 4 2 0
DQ1
23 21 19 17 15 13 11 9 7 5 3 1
9.2.10
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
Except for parallelizing the instruction code and the address on the two pins DQ0 and DQ1,
the instruction functionality is the same as the Sector Erase (SE) instruction of the Extended
SPI protocol.
94/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.