N25Q032A13E1241F Datasheet, PDF (118/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Figure 89. Read Lock Register instruction and data-out sequence QIO-SPI
S
C
DQ0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
*24-bit Address
Lock Register Out
20 16 12 8 4 0 4 0 4 0 4 0 4 0
DQ1
DQ2
21 17 13 9 5 1 5 1 5 1 _{5 1 5 1}
22 18 14 10 6 2 6 2 6 2 6 2 6 2
DQ3
23 19 15 11 7 3 7 3 7 3 7 3 7 3
9.3.17
*Address bits A23 and A22 are “Don’t Care.”
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
Except for the parallelizing of the instruction code, the address and the input data on the
four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the
Write to Lock Register (WRLR) instruction of the Extended SPI protocol.
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