N25Q032A13E1241F Datasheet, PDF (46/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Protection modes
N25Q032 - 3 V
7.2
Specific hardware and software protection
There are two software protected modes, SPM1 and SPM2, that can be combined to protect
the memory array as required. The SPM2 can be locked by hardware with the help of the W
input pin.
SPM1
The first software protected mode (SPM1) is managed by specific Lock Registers assigned
to each 64 Kbyte sector.
The Lock Registers can be read and written using the Read Lock Register (RDLR) and
Write to Lock Register (WRLR) instructions.
In each Lock Register two bits control the protection of each sector: the Write Lock bit and
the Lock Down bit.
z Write Lock bit: The Write Lock bit determines whether the contents of the sector can be
modified (using the Program or Erase instructions). When the Write Lock bit is set to '1',
the sector is write protected - any operations that attempt to change the data in the
sector will fail. When the Write Lock bit is reset to '0', the sector is not write protected by
the Lock Register, and may be modified.
z Lock Down bit: The Lock Down bit provides a mechanism for protecting software data
from simple hacking and malicious attack. When the Lock Down bit is set to '1', further
modification to the Write Lock and Lock Down bits cannot be performed. A powerup is
required before changes to these bits can be made. When the Lock Down bit is reset to
'0', the Write Lock and Lock Down bits can be changed.
The definition of the Lock Register bits is given in Table 19.: Lock Register out.
SPM2
The second software protected mode (SPM2) uses the Block Protect bits (BP2, BP1, BP0)
and the Top/Bottom bit (TB bit) to allow part of the memory to be configured as read-only.
See Section 16: Ordering information.
Table 9. Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity)
Sector Lock Register
Lock Down Write Lock
bit
bit
Protection Status
0
0
Sector unprotected from Program/Erase operations, protection status reversible.
0
1
Sector protected from Program/Erase operations, protection status reversible.
Sector unprotected from Program/Erase operations.
1
0
Sector protection status cannot be changed except by a power-up.
Sector protected from Program/Erase operations.
1
1
Sector protection status cannot be changed except by a power-up.
As a second level of protection, the Write Protect signal (applied on the W/VPP pin) can
freeze the Status Register in a read-only mode. In this mode, the Block Protect bits (BP2,
BP1, BP0), the Top/Bottom (TB) bit, and the Status Register Write Disable bit (SRWD) are
protected.
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