N25Q032A13E1241F Datasheet, PDF(132/153 Page) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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N25Q032A13E1241F Datasheet, PDF (132/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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Power-up and power-down

11 Power-up and power-down

N25Q032 - 3 V

At power-up and power-down, the device must not be selected (that is Chip Select (S) must

follow the voltage applied on VCC) until VCC reaches the correct value:

z VCC(min) at power-up

z VSS at power-down

A safe configuration is provided in Section 3: SPI Modes.

To avoid data corruption and inadvertent write operations during power-up, a Power On

Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less

than the Power On Reset (POR) threshold voltage, VWI - all operations are disabled, and

the device does not respond to any instruction.

During a standard power-up phase the device ignores all the instructions but RDSR and

RFSR (they can be used to check the memory internal state according to Figure 102.:

Power-up timing.

After power-up, the device is in the following state:

z The device is in the Standby Power mode

z The Write Enable Latch (WEL) bit is reset

z The Write In Progress (WIP) bit is reset

z The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0).

Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply.

Each device in a system should have the VCC line decoupled by a suitable capacitor close

to the package pins (generally, this capacitor is of the order of 100 nF).

At power-down, when VCC drops from the operating voltage, to below the Power On Reset

(POR) threshold voltage, VWI, all operations are disabled and the device does not respond

to any instruction (the designer needs to be aware that if power-down occurs while a

Program or Erase cycle is in progress, some data corruption may result).

VPPH must be applied only when VCC is stable and in the VCC(min) to VCC(max) voltage

range.

Figure 102. Power-up timing

Vcc

V CC(m ax)

C h ip s e le c tio n n o t a llo w e d

V CC(m in)

VWI

C h ip

re s e t

tVTW = tVTR

P ollin g allowed

S P I p ro to c o l

W IP = 1

WEL = 0

D evice fu lly accessible

S ta rtin g p ro to c o l d e fin e d b y N V C R

W IP = 0

WEL = 0

tim e

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

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