N25Q032A13E1241F Datasheet, PDF (58/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Figure 12. Read Data Bytes at Higher Speed instruction and data-out sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction
24-bit address*
DQ0
DQ1
High Impedance
23 22 21
3210
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy cycles
DQ0
DQ1
76543210
DATA OUT 1
DATA OUT 2
76543210765432107
MSB
MSB
MSB
*Address bits A23 and A22 are “Don’t Care.”
9.1.4
Note:
Read Serial Flash Discovery Parameter
The Read Serial Flash Discovery Parameter (RDSFDP) instruction allows reading the Serial
Flash Discovery Parameter area (SFDP). This SFDP area is composed of 2048 read-only
bytes containing operating characteristics and vendor specific information. The SFDP area
is factory programmed.
Data to be written to the SFDP area is in definition phase.
If the SFDP area is blank, the device is shipped with all the SFDP bytes at FFh. If only a
portion of the SFDP area is written to, the portion not used is shipped with bytes in erased
state (FFh).
The instruction sequence for RDSFDP has the same structure as that of a Fast Read
instruction. First, the device is selected by driving Chip Select (S) Low. Next, the 8-bit
instruction code (5Ah) and the 24-bit address are shifted in, followed by a configurable
number of dummy clock cycles.
Therefore, the entire SFDP area can be read with a single RDSFDP instruction. When the
highest address (7FFh) is reached, the address counter rolls over to 000h, allowing the read
sequence to be continued indefinitely.
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