N25Q032A13E1241F Datasheet, PDF (113/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Instructions
9.3.9
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been
executed.
Except for the parallelizing of the instruction code and the address on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Subsector Erase
(SSE) instruction of the Extended SPI protocol.
Figure 82. Subsector Erase instruction sequence QIO-SPI
S
C
DQ0
0123456789
Instruction *24-Bit Address
20 16 12 8 4 0
DQ1
21 17 13 9 5 1
DQ2
22 18 14 10 6 2
DQ3
23 19 15 11 7 3
9.3.10
*Address bits A[23:22] are “Don’t Care.”
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
Except for the parallelizing of the instruction code and the address on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Sector Erase
(SE) instruction of the Extended SPI protocol.
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