N25Q032A13E1241F Datasheet, PDF(19/153 Page) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

N25Q032A13E1241F Datasheet, PDF (19/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

◁

N25Q032 - 3 V

SPI Modes

(Cp = parasitic capacitance of the bus line) is shorter than the time during which the bus

master leaves the SPI bus in high impedance.

Example: Cp = 50 pF, that is R*Cp = 5 Âµs <=> the application must ensure that the bus

master never leaves the SPI bus in the high impedance state for a time period shorter than

5 Âµs. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as

appropriate.

Figure 6. SPI modes supported

CPOL CPHA

0

0

C

1

1

C

DQ0

MSB

DQ1

MSB

AI13730

19/153

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Â©2010 Micron Technology, Inc. All rights reserved.

▷