N25Q032A13E1241F Datasheet, PDF(33/153 Page) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

N25Q032A13E1241F Datasheet, PDF (33/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

◁

N25Q032 - 3 V

Volatile and Non Volatile Registers

6.1

Legacy SPI Status Register

The Status Register contains a number of status and control bits that can be read or set by

specific instructions: Read Status Register (RDSR) and Write Status Register (WRSR). This

is available in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI).

Table 2. Status register format

SRWD

BP2

BP1

BP0

WEL

WIP

6.1.1

6.1.2

6.1.3

6.1.4

Status register write protect

Top/bottom bit

Block protect bits

Write enable latch bit

Write in progress bit

WIP bit

The Write In Progress (WIP) bit set to 1 indicates that the memory is busy with a Write

Status Register, Program or Erase cycle. 0 indicates no cycle is in progress.

WEL bit

The Write Enable Latch (WEL) bit set to 1 indicates that the internal Write Enable Latch is

set. When set to 0 the internal Write Enable Latch is reset and no Write Status Register,

Program or Erase instruction is accepted.

Block Protect bits (BP2, BP1, BP0)

The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to

be software protected against Program and Erase instructions. These bits are written with

the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,

BP1, BP0) bits is set to 1, the relevant memory area, as defined in Table 10.: Protected area

sizes, Upper (TB bit = 0) becomes protected against all program and erase instructions. The

Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected

mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block

Protect (BP2, BP1, BP0) bits are 0.

TB bit

The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register

(WRSR) instruction provided that the Write Enable (WREN) instruction has been issued.

33/153

Micron Technology, Inc., reserves the right to change products or specifications without notice.

▷