N25Q032A13E1241F Datasheet, PDF (80/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered in either of the following ways:
z setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/VPP) Low
z driving Write Protect (W/VPP) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W/VPP) High.
If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM2), using the Block Protect
(BP2, BP1, BP0) bits and the Top/Bottom (T/B) bits of the Status Register, can be used.
Table 18. Protection modes
W / VPP SRWD
Signal bit
Mode
Write protection of the status
register
Memory content
Protected area ⁽¹⁾ Unprotected area ⁽¹⁾
1
0
Status register is writeable, if the
0
1
0
1
Software
protected
(SPM2)
WREN instruction has set the WEL
bit.
The values in the SRWD, TB, BP2,
BP1, and BP0 bits can be
Protected against PP,
DIFP, DIEFP, QIFP,
QIEFP, SSE, SE and
BE instructions.
Ready to accept PP,
DIFP, DIEFP, QIFP,
QIEFP, SSE, and SE
instructions.
changed.
0
1
Hardware
protected
(HPM)
Status Register is hardware write
protected. The values in the
SRWD, TB, BP2, BP1 and BP0 bits
cannot be changed
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
SE and BE
instructions.
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
and SE instructions.
1. As defined by the values in the Block Protect (TB, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2: Status
register format.
9.1.25
Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output
(DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of
Serial Clock (C).
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
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