N25Q032A13E1241F Datasheet, PDF (48/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Memory organization
8
Memory organization
N25Q032 - 3 V
The memory is organized as:
z 4,194,304 bytes (8 bits each)
z 64 sectors (64 Kbytes each)
z 1,024 subsectors (4 Kbytes each)
z 16,384 pages (256 bytes each)
z 64 OTP bytes located outside the main memory array
Each page can be individually programmed: bits are programmed from 1 to 0. The device is
Subsector eraseble, Sector eraseble or Bulk Erasable but not Page Erasable: bits are
erased from 0 to 1.
Figure 9. Block diagram
HOLD
W/V_PP
S
C
DQ0
DQ1
Control logic
High voltage
generator
I/O shift register
64 OTP bytes
Address register
and counter
256 byte
data buffer
3FFFFFh
Status
register
48/153
00000h
000FFh
256 bytes (page size)
X decoder
AI13722b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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