N25Q032A13E1241F Datasheet, PDF (96/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Figure 56. Program/Erase Suspend instruction sequence DIO-SPI
S
01234
C
Instruction
DQ0
DQ1
9.2.13
Program/Erase Resume
After a Program/Erase suspend instruction, a Program/Erase Resume instruction is
required to continue performing the suspended Program or Erase sequence.
Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Program/Erase Resume (PER)
instruction of the Extended SPI protocol.
Figure 57. Program/Erase Resume instruction sequence DIO-SPI
S
01234
C
Instruction
DQ0
9.2.14
DQ1
Dual_Program_Erase_Resume
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. Except
for the parallelizing of the instruction code and the output data on the two pins DQ0 and
DQ1, the instruction functionality is exactly the same as the Read Status Register (RDSR)
instruction of the Extended SPI protocol.
96/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.