N25Q032A13E1241F Datasheet, PDF (79/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Instructions
initiated. While the write status register cycle is in progress, the status register may still be
read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1
during the self-timed write status register cycle, and is 0 when it is completed. When the
cycle is completed, the write enable latch (WEL) is reset.
The write status register (WRSR) instruction allows the user to change the values of the
block protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 10.: Protected area sizes, Upper (TB bit = 0) and Table 11.:
Protected area sizes, Lower (TB bit = 1).
The write status register (WRSR) instruction also allows the user to set and reset the status
register write disable (SRWD) bit in accordance with the Write Protect (W/VPP) signal. The
status register write disable (SRWD) bit and Write Protect (W/VPP) signal allow the device
to be put in the hardware protected mode (HPM). The write status register (WRSR)
instruction is not executed once the hardware protected mode (HPM) is entered.
Figure 32. Write Status Register instruction sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction
Status
register in
DQ0
76543210
DQ1
High Impedance
MSB
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/VPP) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to '1', two
cases need to be considered, depending on the state of Write Protect (W/VPP):
z If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
z If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction (attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM2) by the Block Protect (BP2, BP1, BP0) bits and the
Top/Bottom (T/B) bit of the Status Register, are also hardware protected against data
modification.
79/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.