N25Q032A13E1241F Datasheet, PDF (16/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Signal descriptions
N25Q032 - 3 V
2.5
Hold (HOLD) or Reset (Reset)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
Reset functionality is present instead of Hold in devices with a dedicated part number. See
Section 16: Ordering information.
During Hold condition, the Serial Data output (DQ1) is in high impedance, and Serial Data
input (DQ0) and Serial Clock (C) are Don't Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
For devices featuring Reset instead of Hold functionality, the Reset (Reset) input provides a
hardware reset for the memory.
When Reset (Reset) is driven High, the memory is in the normal operating mode. When
Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output
is high impedance.
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost.
In the Extended SPI protocol, during the QOFR, QIOFR, QIFP and the Quad Extended Fast
Program (QIEFP) instructions, the Hold (Reset) / DQ3 is used as an input/output (DQ3
functionality).
In QIO-SPI, the Hold (Reset) / DQ3 pin acts as an I/O (DQ3 functionality), and the HOLD
(Reset) functionality disabled when the device is selected. When the device is deselected (S
signal is high), in parts with Reset functionality, it is possible to reset the device unless this
functionality is not disabled by mean of dedicated registers bits.
The HOLD (Reset) functionality can be disabled using bit 3 of the NVCR or bit 4 of the
VECR.
2.6
Write protect/enhanced program supply voltage (W/VPP),
DQ2
W/VPP/DQ2 can be used as:
z A protection control input.
z A power supply pin.
z I/O in Extended SPI protocol quad instructions and in QIO-SPI protocol instructions.
When the device is operated in Extended SPI protocol with single or dual instructions, the
two functions W or VPP are selected by the voltage range applied to the pin. If the W/VPP
input is kept in a low voltage range (0 V to VCC) the pin is seen as a control input. This input
signal is used to freeze the size of the area of memory that is protected against program or
erase instructions (as specified by the values in the BP[0:3] bits of the Status Register. (See
Table 2.: Status register format).
If VPP is in the range of VPPH, it acts as an additional power supply during the Program or
Erase cycles (See Table 27.: Operating conditions). In this case VPP must be stable until
the Program or Erase algorithm is completed.
During the Extended SPI protocol, the QOFR and QIOFR instructions, and the QIO-SPI
protocol instructions, the pin W/VPP/DQ2 is used as an input/output (DQ2 functionality).
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