N25Q032A13E1241F Datasheet, PDF (138/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

DC and AC parameters
N25Q032 - 3 V
Table 31. AC Characteristics (page 1 of 2)
Symbol
Alt.
Parameter
Min
Clock frequency for the all the
fC
fC
instructions (Extended SPI, DIO-SPI and D.C.
QIO-SPI protocol) but the READ instruction
fR
tCH⁽¹⁾
tCL⁽²⁾
tCLCH⁽³⁾
tCHCL⁽³⁾
tCLH
tCLL
Clock frequency for read instructions
Clock High time
Clock Low time
Clock rise time⁽⁴⁾ (peak to peak)
Clock fall time⁽⁴⁾ (peak to peak)
D.C.
4
4
0.1
0.1
tSLCH
tCSS S active setup time (relative to C)
4
tCHSL
4
tDVCH
tDSU Data in setup time
2
tCHDX
tDH
Data in hold time
3
tCHSH
S active hold time (relative to C)
4
tSHCH
S not active setup time (relative to C)
4
tSHSL
tSHQZ⁽³⁾
tCSH
tDIS
S deselect time after a correct read
instruction
20
S deselect time after a not correct read or
after any different instruction
50
Output disable time
Clock Low to Output valid under 30 pF
tCLQV
tV
Clock Low to Output valid under 10 pF
tCLQX
tHO
Output hold time
1
tHLCH
HOLD setup time (relative to C)
4
tCHHH
HOLD hold time (relative to C)
4
tHHCH
HOLD setup time (relative to C)
4
tCHHL
HOLD hold time (relative to C)
4
tHHQX⁽³⁾ tLZ
HOLD to Output Low-Z
tHLQZ⁽³⁾
tHZ
HOLD to Output High-Z
tWHSL⁽⁵⁾
Write protect setup time
20
tSHWL⁽⁵⁾
Write protect hold time
100
tVPPHSL⁽⁶⁾
Enhanced program supply voltage High
(VPPH) to Chip Select Low for Single and 200
Dual I/O Page Program
tW
Write status register cycle time
tCFSR
Clear flag status register cycle time
Typ⁽²⁾
1.3
40
Max
108
Unit
MHz
54
MHz
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
8
ns
7
ns
5
ns
ns
ns
ns
ns
ns
8
ns
8
ns
ns
ns
ns
8
ms
ns
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