N25Q032A13E1241F Datasheet, PDF (38/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Volatile and Non Volatile Registers
N25Q032 - 3 V
6.3
Volatile Configuration Register
The Volatile Configuration Register (VCR) affects the memory configuration after every
execution of Write Volatile Configuration Register (WRVCR) instruction: this instruction
overwrite the memory configuration set at POR by the Non Volatile Configuration Register
(NVCR). Its purpose is to define the dummy clock cycles number and to make the device
ready to enter in the required XIP mode.
Table 5. Volatile Configuration Register
Bit
Parameter
Binary
Value
Decimal
Value
Description
Dummy
VCR<7:4> clock
cycles ⁽¹⁾
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VCR<3>
VCR<2>
0
XIP ⁽²⁾
1
Reserved x
00
01
VCR<1:0> Wrap
10
11
As '1111'
1
2
3
4
5
6
7
To optimize instruction execution (FASTREAD, DOFR, DIOFR,
QOFR, QIOFR, ROTP, RDSFDP) according to the frequency
8
9
10
11
12
13
14
15
Targets maximum allowed frequency fc (108MHz) and guarantees
backward compatibility (default)
0
Ready to enter XIP mode
1
XIP disabled (default)
reserved Fixed value = 0b
0
16-byte wrap: Output data wraps within an aligned 16-byte boundary
starting from the address issued after the command code.
1
32-byte wrap: Output data wraps within an aligned 32-byte boundary
starting from the address issued after the command code.
2
64-byte wrap: Output data wraps within an aligned 64-byte boundary
starting from the address issued after the command code.
3
Continous reading (Default): All bytes are read sequentially
1. To optimize instruction execution (FASTREAD, DOFR,DIOFR,QOFR, QIOFR, ROTP) according to the frequency.
2. To make the data on DQ0 during the first dummy clock NOT “Don’t Care.” For devices with feature set digit equal to 2 or 4
in the part number (Basic XiP), this bit is always Don't Care."
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