N25Q032A13E1241F Datasheet, PDF (109/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Instructions
Figure 75. Read OTP instruction and data-out sequence QIO-SPI
S
C
DQ0
0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21 22 23
Instruction
20 16 12 8 4 0
Data Data
out 1 out n
404040
DQ1
DQ2
21 17 13 9 5 1
22 18 14 10 6 2
515151
6 26262
DQ3
23 19 15 11 7 3
737373
Dummy (ex.: 10)
9.3.5
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Except for the
parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the
instruction functionality is exactly the same as the Write Enable instruction of the Extended
SPI protocol.
Figure 76. Write Enable instruction sequence QIO-SPI
S
01
C
Instruction
DQ0
DQ1
DQ2
DQ3
Quad_Write_Enable
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