N25Q032A13E1241F Datasheet, PDF(59/153 Page) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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N25Q032A13E1241F Datasheet, PDF (59/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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N25Q032 - 3 V

Instructions

The bytes of SFDP content are shifted out on the Serial Data Output (DQ1) starting from the

specified address. Each bit is shifted out during the falling edge of Serial Clock (C). The

Read SFDP instruction is terminated by driving Chip Select (S) High at any time during data

output.

Any Read Serial Flash Discovery Parameter (RDSFDP) instruction issued while an Erase or

Program cycle is in progress, is rejected without having any effect on the cycle that is in

progress.

Figure 13. Read Serial Flash Discovery Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

Instruction

24-bit address*

DQ0

23 22 21

3210

High Impedance

DQ1

9.1.5

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Dummy cycles

DQ0

DQ1

76543210

DATA OUT 1

DATA OUT 2

76543210765432107

MSB

*Address bits A[23:11] are âDonât Care.â

Dual Output Fast Read (DOFR)

The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at

Higher Speed (FAST_READ) instruction, except that the data are shifted out on two pins

(pin DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one

doubles the data transfer bandwidth compared to the Read Data Bytes at Higher Speed

(FAST_READ) instruction.

The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual

Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a configurable

number of dummy clock cycles, each bit being latched-in during the rising edge of Serial

Clock (C). Then the memory contents, at that address, are shifted out on DQ0 and DQ1 at a

maximum frequency Fc, during the falling edge of Serial Clock (C).

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole

memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction.

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

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