N25Q032A13E1241F Datasheet, PDF(39/153 Page) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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N25Q032A13E1241F Datasheet, PDF (39/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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N25Q032 - 3 V

Volatile and Non Volatile Registers

6.3.1

Note:

6.3.2

6.3.3

Dummy clock cycle: VCR bits 7:4

The bits from 7 to 4 of the Volatile Configuration Register, as the bits from 15 to 12 of the

Non-Volatile Configuration register, set the dummy clock cycles number after the fast read

instructions (in all the 3 available protocols). The dummy clock cycles number can be set

from 1 up to 15 as described in Table 5.: Volatile Configuration Register, according to

operating frequency (the higher is the operating frequency, the bigger must be the dummy

clock cycle number, according to Table 4.: Maximum operative frequency by dummy clock

cycles) to optimize the fast read instructions performance.

If the dummy clock number is not sufficient for the operating frequency, the memory reads

wrong data.

XIP Volatile Configuration bits (VCR bit 3)

The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set to

0 to enable the memory working on XIP mode. For devices with a feature set digit equal to 2

or 4 in the part number (Basic XiP), this bit is always Don't Care, and it is possible to operate

the memory in XIP mode without setting it to 0. See Section 16: Ordering information.

Wrap: VCR bits 1:0

The bits from 1 to 0 allow the Wrap mode to be available for each kind of read instruction

and protocol. A specific setting provides the ability to read the memory from sequentially

(standard) mode to a wrap mode, where the reads can be confined inside the 16, 32, or 64

byte boundary. For Wrap setting options, see Table 5.: Volatile Configuration Register. The

following table shows an example of the sequence of bytes in the 16-byte, 32-byte, and 64-

byte options, according to the starting address.

Table 6. Sequence of Bytes Read during Wrap Mode

Starting Address

16-Byte Wrap

32-Byte Wrap

0-1-2- . . . -15-0-1- . .

0-1-2- . . . -31-0-1- . .

1-2- . . . -15-0-1-2- . .

1-2- . . . -31-0-1-2- . .

15-0-1-2-3- . . . -15-0-1- . . 15-16-17- . . . -31-0-1- . .

31-16-17- . . . -31-16-17- . . 31-0-1-2-3- . . . -31-0-1- . .

63-48-49- . . . -63-48-49- . . 63-32-33- . . . -63-32-33- . .

64-Byte Wrap

0-1-2- . . . -63-0-1- . .

1-2- . . . -63-0-1-2- . .

15-16-17- . . . -63-0-1- . .

31-32-33- . . . -63-0-1- . .

63-0-1- . . . -63-0-1- . .

6.4

Volatile Enhanced Configuration Register

The Volatile Enhanced Configuration Register (VECR) affects the memory configuration

after every execution of Write Volatile Enhanced Configuration Register (WRVECR)

instruction: this instruction overwrite the memory configuration set during the POR

sequence by the Non Volatile Configuration Register (NVCR). Its purpose is:

z enabling of QIO-SPI protocol and DIO-SPI protocol

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

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