N25Q032A13E1241F Datasheet, PDF (116/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Figure 86. Program/Erase Resume instruction sequence QIO-SPI
S
01
C
Instruction
DQ0
DQ1
DQ2
DQ3
9.3.14
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. Except
for the parallelizing of the instruction code and the output data on the four pins DQ0, DQ1,
DQ2 and DQ3, the instruction functionality is exactly the same as the Read Status Register
(RDSR) instruction of the Extended SPI protocol.
Figure 87. Read Status Register instruction sequence QIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
C
Instruction
Status Register Out
DQ0
4040 404040404040
DQ1
5151 515151515151
DQ2
6262 626 262626262
DQ3
7 3 7 3 7 37 3 7 3 7 3 7 37 3
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