N25Q032A13E1241F Datasheet, PDF (87/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Instructions
Figure 42. Write Volatile Enhanced Configuration Register instruction sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction
VECR In
DQ0
76543210
High Impedance
MSB
DQ1
9.2
DIO-SPI Instructions
In DIO-SPI protocol, instructions, addresses and input/Output data always run in parallel on
two wires: DQ0 and DQ1.
In the case of a Dual Command Fast Read (DCFR), Read OTP (ROTP), Read Lock
Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read
NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR),
Read Volatile Enhanced Configuration Register (RDVECR), Read Serial Flash Discovery
Parameter (RDSFDP), and Multiple I/O Read Identification (MIORDID) instruction, the
shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be
driven High after any bit of the data-out sequence is being shifted out.
In the case of a Dual Command Page Program (DCPP), Program OTP (POTP), Subsector
Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Program/Erase Suspend (PES),
Program/Erase Resume (PER), Write Status Register (WRSR), Clear Flag Status Register
(CLFSR), Write to Lock Register (WRLR), Write Volatile Configuration Register (WRVCR),
Write Volatile Enhanced Configuration Register (WRVECR), Write NV Configuration
Register (WRNVCR), Write Enable (WREN) or Write Disable (WRDI) instruction, Chip
Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is
rejected, and is not executed.
All attempts to access the memory array during a Write Status Register cycle, a Write Non
Volatile Configuration Register, a Program cycle, or an Erase cycle are ignored. The internal
Write Status Register cycle, Write Non Volatile Configuration Register, Program cycle, or
Erase cycle continues unaffected. The exception is the Program/Erase Suspend instruction
(PES), that can be used to pause all the Program and Erase cycles, except for the Program
OTP (POTP), the Write Status Register, the Bulk Erase (BE), and the Write Non Volatile
Configuration Register.
The suspended program or erase cycle can be resumed by mean of the Program/Erase
Resume instruction (PER). During the program/erase cycles also the polling instructions (to
check if the internal modify cycle is finished by mean of the WIP bit of the Status Register or
of the Program/Erase controller bit of the Flag Status register) are also accepted to allow the
application checking the end of the internal modify cycles, of course these polling
instructions don't affect the internal cycles performing.
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