N25Q032A13E1241F Datasheet, PDF (97/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Figure 58. Read Status Register instruction sequence DIO-SPI
S
0 1 2 3 4 5 6 7 8 9 10 11
C
Instruction
Status Register Out
Byte
Byte
DQ0
6420 6420
Instructions
9.2.15
DQ1
7531 7531
Dual_Read_SR
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed. Except for the parallelizing of the instruction code and the input data on the
two pins DQ0 and DQ1, the instruction functionality and the protection feature management
is exactly the same as the Write Status Register (WRSR) instruction of the Extended SPI
protocol.
Figure 59. Write Status Register instruction sequence DIO-SPI
S
C
DQ0
01234567
Status Register In
Instruction
Byte
6420
DQ1
7531
9.2.16
*Address bits A[23:22] are “Don’t Care.”
Read Lock Register (RDLR)
The Read Lock Register instruction is used to read the lock register content.
Except for the parallelizing of the instruction code, the address and the output data on the
two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Read Lock
Register (RDLR) instruction of the Extended SPI protocol.
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