N25Q032A13E1241F Datasheet, PDF (40/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Volatile and Non Volatile Registers
N25Q032 - 3 V
Warning: WARNING: in case of both QIO-SPI and DIO-SPI enabled, the
memory works in QIO-SPI
z HOLD (Reset) functionality disabling
z To enable the VPP functionality in Quad I/O modify operations
z To define output driver strength (3 bit)
Table 7. Volatile Enhanced Configuration Register
Bit
Parameter Value
Description
VECR<7>
Quad Input ⁰
Command ₁
Enabled
Disabled (default)
VECR<6>
VECR<5>
Dual Input ⁰
Command ₁
Reserved
x
Enabled
Disabled (default)
Reserved
VECR<4>
Reset/Hold ⁰
disable
1
Disabled
Enabled (default)
VECR<3>
Accelerator 0
pin enable in
QIO-SPI
protocol or in ¹
QIFP/QIEFP
000
Enabled
Disabled (default)
reserved
001
90
010
60
VECR<2:0>
Output Driver ⁰¹¹
Strength
100
45
reserved
101
20
110
15
111
30 (default)
Note
Enable command on four input lines
Enable command on two input lines
Fixed value = 0b
Disable Pad Hold/Reset functionality
The bit must be considered in case of QIFP,
QIEFP, or QIO-SPI protocol. It is “Don’t
Care” otherwise.
Impedance at V_CC/2
6.4.1
Quad Input Command VECR<7>
The Quad Input Command configuration bit can be used to make the memory start working
in QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register
(WRVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI
protocol, If this bit is set to 0 the memory works in QIO-SPI protocol. If VECR bit 7 is set
back to 1 the memory start working again in Extended SPI protocol, unless the bit 6 is set to
0 (in this case the memory start working in DIO-SPI mode).
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7and bit 6 of the
VECR set to 0), the memory will work in QIO-SPI.
40/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.