N25Q032A13E1241F Datasheet, PDF (81/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Instructions
Figure 33. Read Lock Register instruction and data-out sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
*24-bit Address
DQ0
DQ1
High Impedance
23 22 21
MSB
3210
Lock Register Out
76543 210
MSB
*Address bits A23 and A22 are “Don’t Care.”
Table 19. Lock Register out⁽¹⁾
Bit Bit name Value
Function
b7-b2
Reserved
b1
Sector Lock
Down
‘1’
The Write Lock and Lock Down bits cannot be changed. Once a ‘1’ is written to the
Lock Down bit it cannot be cleared to ‘0’, except by a power-up.
‘0’ The Write Lock and Lock Down bits can be changed by writing new values to them.
b0
Sector
Write Lock
‘1’
Program and Erase operations in this sector will not be executed. The memory
contents will not be changed.
‘0’
Program and Erase operations in this sector are executed and will modify the sector
contents.
1. Values of (b1, b0) after power-up are defined in Section 7: Protection modes.
9.1.26
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes (pointing to any address in the
targeted sector and one data byte on Serial Data input (DQ0). The instruction sequence is
shown in Figure 22. Chip Select (S) must be driven High after the eighth bit of the data byte
has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not
executed.
Lock Register bits are volatile, and therefore do not require time to be written. When the
Write to Lock Register (WRLR) instruction has been successfully executed, the Write
Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value.
Any Write to Lock Register (WRLR) instruction, while an Erase or Program cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
81/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.