N25Q032A13E1241F Datasheet, PDF (133/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Power-up and power-down
11.1
Table 25. Power-up timing and V_WI threshold
Symbol
Parameter
t_VTR(1)
t_VTW(1)
V_WI(1)
V_CC(min) to Read
V_CC(min) to device fully accessible
Write inhibit voltage
1. These parameters are characterized only.
Min Max Unit
150 µs
150 µs
1.5
2.5
V
Rescue sequence in case of power loss during WRNVCR
If a power loss occurs during a Write Non Volatile Configuration Register instruction, after
the next power on the device could eventually wake up in a not determined state, for
example a not required protocol or XIP mode. In that case a particular rescue sequence
must be used to recover the device at a fixed state (Extended SPI protocol without XIP) until
the next power up. Then to fix the problem definitively is recommended to run the Write Non
Volatile configuration Register again.
The rescue sequence is composed of two parts that have to be run in the correct order.
During all the sequence the TSHSL must be 50ns at least. The sequence is:
DQ0 (PAD DATA) equal to '1' for:
7 clock cycles within S low (S becomes high before 8th clock cycle)
+ 13 clock cycles within S low S becomes high before 14th clock cycle)
+ 25 clock cycles within S low (S becomes high before 26th clock cycle)
To exit from XIP.
DQ0 (PAD DATA) and DQ3 (PAD HOLD) equal to '1' for:
8 clock cycles within S low (S becomes high before 9th clock cycle) to force Normal SPI
protocol.
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