N25Q032A13E1241F Datasheet, PDF (117/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Instructions
9.3.15
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed.
The instruction code and the input data are sent on four pins DQ0, DQ1, DQ2 and DQ3. The
instruction functionality is exactly the same as the Write Status Register (WRSR) instruction
of the Extended SPI protocol. However, the protection feature management is different. In
particular, once SRWD bit is set to '1' the device enters in the hardware protected mode
(HPM) independently from Write Protect (W/VPP) signal value. To exit the HPM mode is
needed to switch temporarily to the Extended SPI protocol.
Figure 88. Write Status Register instruction sequence QIO-SPI
S
0123
C
Status Register In
DQ0
40
DQ1
51
DQ2
62
DQ3
73
9.3.16
Read Lock Register (RDLR)
The Read Lock Register instruction is used to read the lock register content. Apart from
parallelizing the instruction code, the address, and the output data on four pins (DQ0, DQ1,
DQ2, DQ3) the instruction functionality is the same as the Read Lock Register (RDLR)
instruction of the Extended SPI protocol.
117/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.