N25Q032A13E1241F Datasheet, PDF (108/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
N25Q032 - 3 V
Figure 74. Quad Command Fast Read instruction and data-out sequence QIO-SPI,
EBh
S
Mode 3
C _{Mode 0}
DQ0
0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21 22 23 24 25 26 27
Instruction ^{*24-bit Address}
20 16 12 8 4 0
IO switches from Input to Output
4 0 4 04 0 4 0 4 0 4 0
DQ1
DQ2
21 17 13 9 5 1
22 18 14 10 6 2
515151514040
6 26262624040
DQ3
9.3.4
Note:
23 19 15 11 7 3
737373734040
Dummy (ex.: 10) Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6
*Address bits A23 and A22 are “Don’t Care.”
Read OTP (ROTP)
The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the QIO-SPI
protocol. The instruction functionality is exactly the same as the Read OTP instruction of the
Extended SPI protocol. The only difference is that in the QIO-SPI protocol instruction code,
address and output data are all parallelized on the four pins DQ0, DQ1, DQ2 and DQ3.
The dummy byte bits can not be parallelized: 10 clock cycles are requested to perform the
internal reading operation at highest frequency (108MHz).
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