N25Q032A13E1241F Datasheet, PDF(65/153 Page) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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N25Q032A13E1241F Datasheet, PDF (65/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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N25Q032 - 3 V

Instructions

The Write Enable Latch (WEL) bit is reset under the following conditions:

z Power-up

z Write Disable (WRDI) instruction completion

z Write Status Register (WRSR) instruction completion

z Write to Lock Register (WRLR) instruction completion

z Write Non Volatile Configuration Register (WRNVCR) instruction completion

z Write Volatile Configuration Register (WRVCR) instruction completion

z Write Volatile Enhanced Configuration Register (WRVECR) instruction completion

z Page Program (PP) instruction completion

z Dual Input Fast Program (DIFP) instruction completion

z Dual Input Extended Fast Program (DIEFP) instruction completion

z Quad Input Fast Program (QIFP) instruction completion

z Quad Input Extended Fast Program (QIEFP) instruction completion

z Program OTP (POTP) instruction completion

z Subsector Erase (SSE) instruction completion

z Sector Erase (SE) instruction completion

z Bulk Erase (BE) instruction completion

Figure 20. Write Disable instruction sequence

DQ0

01234567

Instruction

DQ1

High Impedance

9.1.12

Page Program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory

(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction

must previously have been executed. After the Write Enable (WREN) instruction has been

decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by

the instruction code, three address bytes, and at least one data byte on Serial Data input

(DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that

go beyond the end of the current page are programmed from the start address of the same

page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)

must be driven Low for the entire duration of the sequence.

If more than 256 bytes are sent to the device, previously latched data are discarded and the

last 256 data bytes are guaranteed to be programmed correctly within the same page. If less

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

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