N25Q032A13E1241F Datasheet, PDF (114/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Instructions
Figure 83. Sector Erase instruction sequence QIO-SPI
S
C
DQ0
0123456789
Instruction *24-bit Address
20 16 12 8 4 0
DQ1
21 17 13 9 5 1
DQ2
DQ3
22 18 14 10 6 2
23 19 15 11 7 3
N25Q032 - 3 V
9.3.11
*Address bits A[23:22] are “Don’t Care.”
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed.
Except for parallelizing the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the
instruction functionality is exactly the same as the Bulk Erase (BE) instruction of the
Extended SPI protocol.
Figure 84. Bulk Erase instruction sequence QIO-SPI
S
C
DQ0
01
Instruction
DQ1
DQ2
DQ3
9.3.12
Program/Erase Suspend
The Program/Erase Suspend (PES) instruction allows the controller to interrupt a Program
or an Erase instruction. In particular, Subsector Erase (SSE), Sector Erase (SE), and Dual
Command Page Program (DCPP) can be suspended and resumed while Bulk Erase (BE),
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