N25Q032A13E1241F Datasheet, PDF (119/153 Pages) Micron Technology – 32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

N25Q032 - 3 V
Figure 90. Write to Lock Register instruction sequence QIO-SPI
S
0123456789
C
Instruction *24-bit Address
Lock Register In
DQ0
20 16 12 8 4 0 4 0
DQ1
21 17 13 9 5 1 5 1
DQ2
22 18 14 10 6 2 6 2
DQ3
23 19 15 11 7 3 7 3
Instructions
9.3.18
*Address bits A23 and A22 are “Don’t Care.”
Read Flag Status Register
The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be
read.
Except for the parallelizing of the instruction code and the output data on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Read Flag
Status Register (RFSR) instruction of the Extended SPI protocol.
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